ADMS Signals: Nets of User-defined Type in Standard SystemVerilog for Event-driven Analog Modeling
A common requirement in digital-dominated mixed-signal verification is the need for purely event-driven models that imitate Spice or AMS blocks at low fidelity but high speed. Resolved record types are commonly used for this modeling style in VHDL-based flows. Unfortunately, SystemVerilog defines only one resolved net type, the logic type. A second, non-standard net type, wreal, has been borrowed from Verilog-AMS and, with proprietary extensions, added to some implementations of SystemVerilog. wreal is a single real value with a small, fixed set of resolution functions. It solves only a subset of the problems commonly encountered in event-driven analog modeling. In contrast, the ADMS_signals approach is completely general and extensible while still conforming strictly to the IEEE SystemVerilog standard. The stored data type can be any type that is legal in SystemVerilog, including arrays and structs (nested to arbitrary depth) and even class instances (objects). The resolution function is a user-supplied SystemVerilog function. Different networks in the same design hierarchy may be given distinct stored type and resolution function.
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