Addressing Today's Complex Clock Modeling Issues with Veloce Emulation Technology
A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use of System-on-Chip (SoC), designs are becoming extremely complex, with an increasing number of peripherals/external interfaces to consider, requiring higher numbers of asynchronous clocks.
Asynchronous clocks allow designers to reuse peripheral IP as well as implement power save states, but doing this brings additional verification challenges for design and verification houses. Emulation becomes essential if the complexity increases beyond two clock domains.
This white paper highlights different types of emulators and brings to light various situations to help users select the appropriate verification tools.
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