The verification of the complex design requires constraint driven random verification enabled testbenches to ensure full functional coverage and random scenarios. But the usage of high level of constraints causes higher simulation times for system level verification, and this has a big impact on overall design cycle time. This paper describes a framework where advance HVL based testbench can be reused to generate the hardware acceleration platform to overcome simulation speed bottleneck and save bring up time of such effort. The various schemes to maximize the performance of hardware acceleration solution are also mentioned in the paper.