Achieving Unprecedented Cost and Performance for Applications Requiring Multiplexed, High-Resolution ADC Functionality
Analog-to-digital converters (ADCs) have long been a key linchpin element in the design of critical systems for many scientific, industrial, medical, and consumer applications, and designers are always looking for more cost-effective methods of achieving desired results from data converter circuits.
Traditionally, many high-performance applications using ADCs have been designed around devices using a successive approximation register (SAR) architecture. This approach has a number of limitations, including steep board space and power requirements. The sensitivity of SAR devices to noise and their low DNL performance increase the need for support circuitry and often drive up design cost and complexity.
In contrast, ADCs using Delta-Sigma architectures are able to deliver high DNL and noise performance with much less complex support circuitry. Until recently, Delta-Sigma ADCs had not been considered appropriate for use in high-performance applications requiring low latency and high conversion rates, for the purpose of achieving wide signal bandwidth. This paper demonstrates, however, with test data, that this “conventional wisdom” no longer holds true. It also introduces the new CS556x/7x/8x family of high-throughput data converters.
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