Achieving Timing Closure with Bluespec SystemVerilog
Achieving timing closure becomes increasingly difficult with more aggressive technologies at higher clock speeds. Today’s designer, typically coding in RTL using Verilog or VHDL, is accustomed to making fine-grained, controlled changes to the RTL, with reasonably predictable consequences as it is taken through synthesis and physical design tools, so that the design’s timing improves continuously until the target is met.
In this document we describe some of the techniques used by the Bluespec SystemVerilog (BSV) designer to achieve timing closure. Most of them will be quite familiar to the RTL designer, but BSV makes some of them much easier to accomplish, and much more likely to be correct.
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