Achieving DFT ClosureThe Next Step in Design For Test
EDA tools have dramatically improved the productivity of conventional ASIC design flows by enabling rapid, predictable and repeatable constraint closure. The industry’s adoption of powerful design methodologies such as formal verification, static timing analysis and new technologies such as physical synthesis are speeding the implementation and verification of multi-million gate ASICs and Systems-on-Chip (SoCs). Relative to manufacturing test, the exponential growth in size and complexity of these devices, coupled with increasingly stringent quality mandates, demands new approaches in design-for-testability (DFT) that must go beyond today’s state-of-the-art.
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