Achieving Design Closure with Constraint-Driven Synthesis
As the use of FPGAs continues to become the hardware design engineer’s choice for implementing custom logic and Intellectual Property (IP), there is an ever-growing need for the EDA industry to standardize on a common constraint language. This standardization will ensure interoperability between FPGA synthesis and place-and-route tools, and will allow accurate description of “designer intent” to achieve design closure. This paper explains how the use of a common constraint language (SDC) to set up constraints will expedite your next FPGA design.
Please disable any pop-up blockers for proper viewing of this Whitepaper.