Achieve Faster Timing Closure with Graph-Based Physical Synthesis
Advances in FPGA technology have opened the door wide open for use in all types of applications, including wireless communications, computer, industrial, defense/aerospace, medical, automotive, and even consumer. Xilinx® Virtex™-4 devices have the capacity, performance, and cost structure to lead a migration from traditional cell-based ASICs to programmable devices in all but the highest volume and bleeding-edge applications. Along with this capability, however, are new challenges from a designer’s perspective. In this article, I’ll discuss a solution to one of these most important challenges—timing closure.
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