An effective DDR memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system. This whitepaper explains the concept of the read reorder buffer (RRB) and how it can improve memory bandwidth. The paper offers experimental results showing how different DRAM controller architectures can achieve DRAM bus utilizations of 10%, 66%, or 100% from the same input traffic stream, depending on whether the architecture has no RRB, an RRB with external scheduling, or an RRB with content-addressable memory (CAM)-based scheduling.