Multicore processor-based systems are the future of embedded computing in high-performance hand-held and power-hungry devices. The ARM Cortex-A9 MPCore multicore processor is ideally poised to meet this demand for System-on-Chip (SoC) designs that embed such processors. The sheer size of such SoCs powered by the ARM Cortex-A9 MPCore multicore processor will make it difficult to manage traditional tasks such as design partitioning, time budgeting, hierarchy management, block shaping, power planning, etc. With time-to-market pressures shrinking the design time, SoC implementers are turning to hierarchical chip planning and finishing systems to automate these traditional tasks and provide them with faster ways to achieve quality floorplans to close their designs.

This article will describe the quad-core hierarchical implementation of ARM’s latest Cortex-A9 MPCore multicore processor using Hydra, Magma’s automated hierarchical design solution. New technologies, features and the ability to provide hand-off quality floorplans in different stages of the design cycle and early-prototyping-to-finalimplementation stages will be discussed.

Reprinted in its entirety from ARM IQ Vol. 7, No. 3, 2008