Design verification is taking an increasing proportion of the SoC design cycle. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems. Running regression suites against the design can take up to several years of CPU time to complete. In this paper, we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system-level verification.

Note: By clicking on the above link, this paper will be emailed to your TechOnLine log-in address by Mentor Graphics.