Accelerating Design Closure with Assertion-Based Verification
Today’s families of complex field programmable gate arrays (FPGAs) allow designers to roll their own system-on-a-chip (SoC) design by giving them access to large, embedded IP blocks, such as processors, memory, and complex I/O structures. This spiraling increase in complexity drives the need for new approaches to complex FPGA design and verification. This paper discusses how assertion-based verification (ABV) has emerged as a major player within this convergent design and verification flow.
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