This paper explores the verification of DSP and communication system Systems-on-Chip (SoC’s) using a typical signal processing system subsystem—in this case a very large parallel digital FIR filter—using MATLABTM from The MathWorks in an interoperable manner with a very high performance emulation system. The results are presented here using Mentor Graphics’ Veloce emulator and its TestBench Xpress (TBX) SceMi2.0 compliant transaction-based hardware acceleration application.

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