The 2005 EDA Branding Study shows that 71% of FPGA projects have difficulty meeting their timing budgets. Several strategies exist to help you meet your timing goals, such as HDL code changes and synthesis and implementation tools settings. In this article, we’ll describe the Xplorer implementation tools strategy to maximize design performance, whether you are evaluating the best achievable performance for a specified clock domain or attempting to meet timing requirements for designs with user constraints.

Reprinted with permission from Xcell Journal / Fourth Quarter 2005. Article © Xcell Journal.