A Tutorial: Phase Locked Loops in DSP Based Modems
To demodulate a received signal, a modem must synchronize the frequency and phase of the final down converter to that of the received carrier. Similarly, in order to detect the modulated signal, the modem must synchronize the frequency and phase of the symbol clock. Traditionally the phase locked loop (PLL) and the control of these loops is performed in the analog domain through voltage controlled oscillators (VCO). In modern receivers, the PLL is implemented in the sampled data domain using DSP techniques.
To understand the synchronization process we must first have an understanding of the behavior of the PLL. At its simplest implementation the PLL is formed by three simple subsystems. These subsystems are a phase detector, a loop filter, and a controllable oscillator. This remarkable system is both delightfully simple and deceptively complicated. It can be both because it is a non-linear control system that operates in very different modes. These modes include locked, locked but pulling out of lock, unlocked but pulling into lock, and unlocked and not pulling into lock. We will first derive the structure of the PLL and review its linear model behavior in the time and frequency domain. We will then examine its behavior its non-linear modes. This paper includes continuous domain and DSP based versions of the PLL.
Please disable any pop-up blockers for proper viewing of this Whitepaper.