A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation
This paper introduces a novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced data set.
Note: By clicking on the above link, this paper will be emailed to your EE Times log-in address by Mentor Graphics.
Please disable any pop-up blockers for proper viewing of this Whitepaper.