Advanced CMOS technology can enable high levels of performance with reduced active power at the expense of increased standby leakage. Scaling device geometries have caused leakage-power consumption to be one of the major challenges of deep sub-micron design and a major source for parametric yield loss. Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. The identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications.