A Programming Model for Heterogeneous Intel x86 Platforms
The client computing platform is moving towards a heterogeneous architecture that consists of a combination of cores focused on scalar performance, and of a set of throughput-oriented cores. The throughput-oriented cores (such as those in the Intel microarchitecture codename Larrabee processor) may be connected over both coherent and non-coherent interconnects, and they may have different instruction set architectures (ISAs). This article describes a programming model for such heterogeneous platforms. It also looks at the language constructs, runtime implementation, and the memory model for such a programming environment.
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