Model-based optical proximity correction (OPC) is an indispensable production tool enabling successful extension of photolithography down to the sub-80nm level. Commercial OPC software has established clear procedures to produce accurate OPC models at best focus condition. However, OPC models calibrated at the best focus condition sometimes fail to prevent catastrophic circuit failure due to patterning short and open caused by accidental shifts of dose and focus within the corners of allowed process windows.

This paper presents a novel model-based OPC verification methodology that precisely pinpoints post-OPC photolithography failures in VLSI circuits through the entire lithographic process window. By application of a critical photolithography process window model in OPC verification software, one can successfully uncover all weak points of a design prior to tape out, eliminating the risk of circuits open and shorts at the extreme corner of the lithographic process.

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