A Novel Bus Arbiter
A novel implementation of an efficient, low-latency and fair bus arbiter with a field programmable gate array (FPGA) is discussed in this paper. In an ATM switch or an IP access server, a common data bus is used to deliver packets or ATM cells between many agents. This is generally the occasion of back-plane application. Arbitration architecture and algorithm are given more discussion with several illustrations. An example of field application also is given.
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