Redundant cell adders are based on the usage of a carry-tree that produces carries into appropriate bit positions without back-propagation. They are the fastest known addition circuits.


This paper presents a new, extremely fast adder for double-precision mantissas (IEEE 754-floating point standard) using 0.6µM CMOS Austria Mikro Systeme Standard Cells. It is a modification of the Kantabutra’s-style-redundant cell adder. This new adder utilizes 46% less silicon area and 29% less power than the original adder, and is even slightly faster due to lower circuit loads and shorter routing.