Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple design rules. Design rule checking (DRC) enforced these manufacturing constraints by comparing a characteristic measurement to a threshold value. Layout patterns either passed or failed these checks, with failures being fixed to ensure a DRC-clean sign-off.

Then along came nanometer process technology, where increasing rates of silicon failure and longer yield ramps initiated a sea change in how designers deal with process constraints. Designers now find they can no longer adequately describe the effects of process limitations and variations with design rules alone. Most urgently, compliance with design rules no longer always guarantees acceptable yields. This paper explains why this is happening and offers a solution in the form of a re-architected DRC processing engine.

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