A Hybrid interconnect approach for GALS NoC systems
The era of many hundreds of millions of transistors within a single chip made multicores and wide functionality SoCs the current popular way of a chip’s architecture and design. This architectural approach is now on a continuous race for improvements, as higher marks of performance are needed every day. As long as these architecture improvements/enhancements continue to relay on the “old” chassis they will suffer from an obvious bottleneck—the main interconnect. That’s due to its connection to all IPs and its role of servicing as the main path for data transportation within the chip.
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