The number of embedded memories contained within an SoC continues to grow rapidly. This growth has driven the need for rethinking manufacturing test strategies as embedded memories represent in most cases a die’s largest contributor to yield loss due to the very large area and density of these regular circuits. A successful memory strategy must incorporate some form of repair methodology in order to achieve profitable yield levels. This paper explores how to formulate an effective repair methodology by leveraging available memory redundancy schemes and advanced on-chip memory repair capabilities. The adaptation of memory repair techniques to the increasing use of power management schemes such as voltage and power islands is also examined.

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