Implementation of the high-performance, fully synthesizable ARM Cortex-A8 processor requires an advanced RTL-to-GDSII (Register Transfer Level-to-Graphic Data System II) methodology. Today’s complete design flow must enable trade-offs between performance, power, and area, as well as the use of strength-based, accurate delay models to concurrently optimize sizing and buffering at the global level to enhance timing predictability and quality of results (QoR). It may also involve the use of advanced datapath optimization techniques that benefit arithmetic-intensive sections. To minimize timing degradation and enable timing closure, the implementation system must perform crosstalk avoidance using accurate common-path pessimism values and use a native margin-less approach to on-chip
variation (OCV) inclusion. The flow must also eliminate time-consuming manual tweaks.

This article discusses how the Magma Talus platform totally automates the implementation of the ARM Cortex-A8 processors and addresses all of the above requirements.

Reprinted in its entirety from ARM IQ Vol. 6, No. 3, 2007