For a viewer of fisheye images, such distortion can be both unusual and confusing. Therefore, it is desirable that the images captured by fisheye cameras be corrected to approximately rectilinear versions before being presented to viewers in applications such as automobile rear-view cameras. For cases where the basic camera parameters are known, correcting fisheye distortion is relatively straightforward mathematically. However, given the intensive computations involved, it cannot be easily implemented on a FPGA.


This paper discusses an innovative architecture developed by Altera and Manipal Dot Net (MDN) to perform fisheye correction on a FPGA when basic camera parameters are known.