As asynchronous clocks are commonplace in today’s ICs, designers need a solution for verifying that a design’s functionality is not impacted by the non-deterministic effects of metastability. This paper describes why metastability occurs in designs with asynchronous clocks and analyzes the various methods that designers use to verify that a design is resilient. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in Mentor Graphics’ clock-domain-crossing verification solution. It also presents a complete verification methodology, describing how designers can use this accurate model of metastability in their RTL simulations.

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