Chip and verification complexities continue to grow. Despite these growing complexities, time-to-market pressures require that chip verification be completed on schedule. Hardware-assisted verification is used primarily to reduce risk by running more verification in a given time. Successfully completing this type of verification depends on three main parameters: performance of the verification engine; quickly adopting the changes in RTL, IP, or peripheral interfaces; and emulating the behavior of the target environment. Ease-of-use, synergy with existing verification environments, and interoperability with software simulators are also contributing factors to successful hardware-assisted verification. This paper discusses the latest developments in Veloce’s highly optimized emulation SoC technology. It explores how Veloce’s unique architecture gives users the flexibility to build highly productive verification environments through the implementation of a hardware stimulus, a software stimulus, or a combination of the two.

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