This paper documents the results of a critical area and critical feature analysis study of four LSI production 90 nm designs. The recommended rule adherence and statistical sensitivity to random particle defects were evaluated and used to prioritize the yield issues of IP, memories and routing within the various products. Automated correction of recommended rule violations was run in the logic routing to quantify the amount of optimization possible without re-routing the chips. Comparisons were done between the chips to identify commonalities and differences in different design implementations

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