A Case for Nonuniform Fault Tolerance in Emerging Memories
As DRAM systems face scalability challenges, the architecture community has started investigating alternative technologies for main memory. These emerging memory technologies tend to suffer from the problem of limited write endurance. We propose to reduce the storage required for error correction by exploiting the observation that only a few lines require high levels of hard-error correction. Additionally, we propose Pay-As-You-Go (PAYG), an efficient hard-error resilient architecture that allocates error correction entries in proportion to the number of hard faults in the line.
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