A Bandwidth Conservation Scheme in PCI-X
PCI-X is a relatively new protocol that holds much promise for high-speed bus communication. This paper presents significant additions to the PCI-X 1.0 version of the protocol (for PCI-X 133 devices only) that would permit them to work at 133Mhz, even in the presence of a PCI-X 66 device on the same bus. This essentially leads to complete utilization of the bandwidth capability of the PCI-X bus when a slower device (PCI-X 66) is also present on the same bus segment. The most significant feature of this protocol is that it would be selectively visible only to PCI-X 133 devices on the bus.
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