Capturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is especially true when each substrate is built using a different methodology, team, and/or format. For silicon interposers, it is common to have the connectivity captured as a Verilog netlist. Whereas, in organic packages, the connectivity is captured in a spreadsheet CSV format. Designers need an EDA platform that can aggregate the different formats for a multi-substrate system and generate a system-level netlist that drives assembly verification.