As clock frequencies and data rates soar, system designers are being forced to account for the effects of degraded high-frequency signals, causing otherwise healthy signals to be potentially unrecognizable at receiver ICs. This technical paper will focus on simulation-based signal-integrity analysis of multi-gigabit interconnects using Mentor Graphics’ HyperLynx GHz product. Techniques will be presented for using both HSPICE and IBIS buffer models in concurrent simulations; along with eye-diagram and jitter analysis using multi-bit stimuli, while accounting for line loss, inter-symbol interference, and advanced via modeling.

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