In this paper, we demonstrate the patterning of active layer for 22 nm planar transistor device and discuss achievements and challenges in 22 nm lithographic printing. Key issues identified include printing tight pitches and 2-D features simultaneously without sacrificing the cell size, while maintaining large process window. For the case of 2-D features, control of the corner rounding is of interest since the gate width over the active region may vary by the tool overlay.

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