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A Significant Technology Advancement in High-Speed Link Modeling and Simulation
by Altera
Technical Paper
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Optimizing DDR Memory Subsystem Efficiency Part 2: A Mobile Application Processor Case Study
by Synopsys
Technical Paper
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Examples of Physical and Scalable SPICE Models for Modern Power Electronic Devices
Technical Paper
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Fundamentals of Component Data Management
Course
6 comments
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Optimizing DDR Memory Subsystem Efficiency Part 1: The Unpredictable Memory Bottleneck
by Synopsys
Technical Paper
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Accelerating DO-254 Approval with Cadence Tools
Technical Paper
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Addressing the "Power-Aware" Challenges of Memory Interface Designs
Technical Paper
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Connectivity for Next-Generation Mobility
Technical Paper / Product Paper
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Physical Design Data Validation from Cell Design to Tapeout
Technical Paper
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A Guide to the MISRA Coding Standard: What You Need to Know
Technical Paper
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Robust Latch-Up Protection with Schematic Netlist Verification
Technical Paper
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Using Baluns and RF Components for Impedance Matching
Technical Paper / Application Note
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Configurable, Easy-to-Use, Packaged Reliability Checks
Technical Paper
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FEATUREDRobust Latch-Up Protection with Schematic Netlist Verification
Technical Paper 605 KB Posted on: Jun 4, 2019
0 likes
FEATUREDConnectivity for Next-Generation Mobility
Technical Paper / Product Paper 1.63 MB Posted on: Mar 14, 2019
0 likes
FEATUREDQuick Solutions for IoT Applications
Digital Processing > Microcontroller
Course 48 min. Posted on: Sep 28, 2018
0 likes
FEATUREDThe Road to Autonomous Driving
Components | Packaging > Sensors/Transducers
Technical Paper 1.33 MB Posted on: Mar 21, 2018
0 likes
FEATUREDPhysical Design Data Validation from Cell Design to Tapeout
Technical Paper 1.06 MB Posted on: Nov 16, 2017
0 likes
FEATUREDAdvancing the Art of Parasitic Extraction
Technical Paper 1.54 MB Posted on: Nov 13, 2017
0 likes
FEATUREDTrue Costs of Process Node Migration
Technical Paper 1.62 MB Posted on: Nov 16, 2017
0 likes
FEATUREDDO-254 Explained
EDA | IP > System Design Tools/Methodologies
Technical Paper 222 KB Posted on: Nov 17, 2016
1 likes
FEATUREDDriving Intelligence to the IoT Edge
EDA | IP > Sensors/Transducers
Technical Paper 4.56 MB Posted on: Mar 29, 2017
0 likes
FEATUREDAccelerating DO-254 Approval with Cadence Tools
Technical Paper 390 KB Posted on: Nov 17, 2016
0 likes
FEATUREDA Guide to the MISRA Coding Standard: What You Need to Know
Software > Programming Languages
Technical Paper 373 KB Posted on: Mar 30, 2017
0 likes
FEATUREDOptimizing DDR Memory Subsystem Efficiency Part 2: A Mobile Application Processor Case Study
by Synopsys
Technical Paper 2.70 MB Posted on: Mar 10, 2016
0 likes
FEATUREDOptimizing DDR Memory Subsystem Efficiency Part 1: The Unpredictable Memory Bottleneck
by Synopsys
Technical Paper 1.95 MB Posted on: Mar 10, 2016
0 likes
FEATUREDA Significant Technology Advancement in High-Speed Link Modeling and Simulation
by Altera
Technical Paper 2.10 MB Posted on: Mar 12, 2014
0 likes
FEATUREDAddressing the "Power-Aware" Challenges of Memory Interface Designs
Technical Paper 1.40 MB Posted on: Aug 2, 2013
0 likes
FEATUREDUsing Baluns and RF Components for Impedance Matching
Components | Packaging > Passives
Technical Paper / Application Note 118 KB Posted on: Jun 2, 2017
0 likes
Fundamentals of Component Data Management
Course 45 min. Posted on: Dec 15, 2010
0 likes
Fundamentals of Accelerated Functional Verification
by TechOnline
Course 45 min. Posted on: Oct 6, 2010
0 likes
The Electrifying Side of AUTOSAR: The Case for Using the ECU Resource Template
Technical Paper 2.02 MB Posted on: Aug 10, 2010
0 likes
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