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Don't Let Power Supply Design be an Afterthought
Webinar
0 comments
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Raising the Efficiency of Power-Factor Correction, from Standby to Full Load
Technical Paper
0 comments
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42V Quad Monolithic Synchronous Step-Down Regulator with 30μA Quiescent Current
Technical Paper
0 comments
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Doing More with Buck Regulator ICs
Technical Paper
0 comments
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Control the Voltage of a Remote Load over Any Length of Copper Wire
Technical Paper / Application Note
0 comments
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A Paradigm Shift in Benchmarking Wi−Fi Performance
Technical Paper
0 comments
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How to Design With a Dual Mode Linear Regulator
Technical Paper
0 comments
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Redefining Power Management through High-voltage Innovation
Technical Paper
0 comments
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60V, Synchronous Step-Down High Current LED Driver
Technical Paper / Application Note
0 comments
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New Linear Regulators Solve Old Problems
Technical Paper / Product Paper
0 comments
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Scalable Industrial Ethernet to Accelerate Industry 4.0
Webinar
0 comments
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Keeping Pace with Power Hungry Mobile Devices
Technical Paper
0 comments
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Understanding LDOs and Their Key Performance Parameters
Technical Paper
0 comments
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Industry's First 0.8uVRMS Noise LDO Has 79dB Power Supply Rejection Ratio at 1MHz
Technical Paper / Application Note
0 comments
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Rugged IO-Link Solutions
Technical Paper / Product Paper
0 comments
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Stay Ahead of Efficiency Regulations for Power Adapters
Technical Paper
0 comments
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How to Charge Capacitive Loads with eFuses
Technical Paper
0 comments
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The Designer’s Guide to: Common Considerations When Selecting a MHz Crystal
Technical Paper
0 comments
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Aligning Automotive Safety Requirements Between IP and SoCs
Technical Paper
0 comments
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Inside a New Architecture for USB Type-C Applications
Technical Paper
0 comments
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Dual 13A μModule Regulator with Digital Interface for Remote Monitoring and Control of Power
Technical Paper / Application Note
0 comments
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Providing a fully digitalized strategy that integrates PCB and mechanical flows
Technical Paper
0 comments
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Fundamentals of Choosing Power-Distribution Topologies and Regulators
Course
1 comments
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Date Range
FEATUREDAchieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer
Technical Paper
887 KB
Posted on: Aug 21, 2013
0 likes
FEATUREDHigh Throughput GSPS Signal Processing Using Synthesizable IP Cores
Technical Paper
120 KB
Posted on: Mar 31, 2014
0 likes
FEATUREDAdvanced Power and Performance Optimization for Multicore SoCs
Technical Paper
1.81 MB
Posted on: May 9, 2014
0 likes
FEATUREDSolving the ASIC Prototype Partition Problem with Synopsys ProtoCompiler
Technical Paper / Product Paper
369 KB
Posted on: Jun 25, 2014
1 likes
FEATUREDReliability, Availability and Serviceability (RAS) for Memory Interfaces
Technical Paper
209 KB
Posted on: Aug 12, 2014
0 likes
FEATUREDPCI Express 4.0 Controller Design and Integration Challenges
Technical Paper
194 KB
Posted on: May 15, 2015
0 likes
FEATUREDRapid Architectural Exploration in Designing Application-Specific Processors
Technical Paper
741 KB
Posted on: May 22, 2015
0 likes
FEATUREDUsing an Embedded Vision Processor to Build an Efficient Object Recognition System
Technical Paper
1.07 MB
Posted on: May 29, 2015
0 likes
FEATUREDOptimizing LPDDR4 Performance and Power with Multi-Channel Architectures
Technical Paper
1.01 MB
Posted on: Feb 11, 2016
0 likes
FEATUREDOptimizing DDR Memory Subsystem Efficiency Part 1: The Unpredictable Memory Bottleneck
Technical Paper
1.95 MB
Posted on: Mar 10, 2016
0 likes
FEATUREDOptimizing DDR Memory Subsystem Efficiency Part 2: A Mobile Application Processor Case Study
Technical Paper
2.70 MB
Posted on: Mar 10, 2016
0 likes
FEATUREDAssessing ESD Sensitivity of Interface IP Using Charged Device Model
Technical Paper
282 KB
Posted on: Jan 9, 2017
0 likes
FEATUREDOptimizing SMIC 40LL and 40ULP Designs for Speed and Energy Efficiency
Webinar
Posted on: Jan 10, 2018
0 likes
FEATUREDARC HS4x and HS4xD CPUs: New Dual-Issue Architecture Boosts Embedded Processor Performance
Technical Paper
1.06 MB
Posted on: Jun 28, 2017
0 likes
Tips for Using Synplify Pro to Improve Altera Device Performance
Technical Paper / Product Paper
77 KB
Posted on: Mar 31, 2006
0 likes
Design Practices and Strategies for Efficient Signal Integrity Closure
Technical Paper
144 KB
Posted on: Nov 12, 2004
0 likes
A Reference Verification Methodology for Vera
Technical Paper
98 KB
Posted on: Oct 6, 2004
0 likes
Integration of Vera and System Studio
Technical Paper
1.12 MB
Posted on: Oct 6, 2004
0 likes
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