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Redefining Power Management through High-voltage Innovation
Technical Paper
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Understanding LDOs and Their Key Performance Parameters
Technical Paper
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Raising the Efficiency of Power-Factor Correction, from Standby to Full Load
Technical Paper
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Providing a fully digitalized strategy that integrates PCB and mechanical flows
by Siemens AG
Technical Paper
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How Serial Flash Technology is Evolving to Meet the New Requirements of AIoT Designs
by Winbond
Webinar
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Dual 13A μModule Regulator with Digital Interface for Remote Monitoring and Control of Power
Technical Paper / Application Note
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Inside a New Architecture for USB Type-C Applications
Technical Paper
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Fundamentals of Choosing Power-Distribution Topologies and Regulators
Course
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Control the Voltage of a Remote Load over Any Length of Copper Wire
Technical Paper / Application Note
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60V, Synchronous Step-Down High Current LED Driver
Technical Paper / Application Note
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42V Quad Monolithic Synchronous Step-Down Regulator with 30μA Quiescent Current
Technical Paper
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Industry's First 0.8uVRMS Noise LDO Has 79dB Power Supply Rejection Ratio at 1MHz
Technical Paper / Application Note
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The Designer’s Guide to: Common Considerations When Selecting a MHz Crystal
Technical Paper
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New Linear Regulators Solve Old Problems
Technical Paper / Product Paper
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Design Practices and Strategies for Efficient Signal Integrity Closure
by Synopsys
Technical Paper 144 KB Posted on: Nov 12, 2004
0 likes
Power Management in Complex SoC Design
by Synopsys
Technical Paper 438 KB Posted on: Nov 16, 2004
0 likes
Designing Using the AMBA 3 AXI Protocol
by Synopsys
Technical Paper 269 KB Posted on: Apr 28, 2005
1 likes
Size Matters! How a System Perspective Slashes the Size of a USB 2.0 Device Core
by Synopsys
Technical Paper 755 KB Posted on: Jul 17, 2002
0 likes
Discovery AMS Full-Chip Verification of Mixed-Signal Designs
by Synopsys
Technical Paper 656 KB Posted on: Oct 5, 2004
0 likes
A Reference Verification Methodology for Vera
by Synopsys
Technical Paper 98 KB Posted on: Oct 6, 2004
0 likes
Integration of Vera and System Studio
by Synopsys
Technical Paper 1.12 MB Posted on: Oct 6, 2004
0 likes
Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
Digital Processing > Networking
by Synopsys
Technical Paper Posted on: Mar 20, 2006
0 likes
Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
by Synopsys
Technical Paper 91 KB Posted on: Mar 20, 2006
0 likes
SystemVerilog for e ExpertsUnderstanding the Migration Process
by Synopsys
Technical Paper 161 KB Posted on: May 26, 2006
0 likes
Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design
by Synopsys
Technical Paper 87 KB Posted on: Sep 29, 2006
0 likes
Efficient Development of Wireless IP with High Level Modeling and Synthesis
Digital Processing > Networking
by Synopsys
Technical Paper 237 KB Posted on: Jun 29, 2006
0 likes
Infusing Speed and Visibility into ASIC Verification
Digital Processing > ASICs/SoCs
by Synopsys
Technical Paper 669 KB Posted on: Jan 5, 2007
0 likes
Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies
by Synopsys
Technical Paper 193 KB Posted on: Jun 19, 2008
0 likes
Life Begins at 65—Unless You Are Mixed Signal?
by Synopsys
Technical Paper 376 KB Posted on: Jul 28, 2008
0 likes
DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs
by Synopsys
Technical Paper 847 KB Posted on: May 19, 2008
0 likes
HapsTrak — A Key to Success
Digital Processing > ASICs/SoCs
by Synopsys
Technical Paper 731 KB Posted on: Nov 1, 2007
0 likes
Synopsys Eclypse Low Power Solution
by Synopsys
Technical Paper 887 KB Posted on: Dec 17, 2008
0 likes
System Level Performance Analysis with Formal Methods and Virtual Prototyping
Digital Processing > ASICs/SoCs
by Synopsys
Technical Paper 2.40 MB Posted on: Sep 26, 2008
0 likes
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