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Keeping Pace with Power Hungry Mobile Devices
Technical Paper
0 comments
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Redefining Power Management through High-voltage Innovation
Technical Paper
0 comments
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Don't Let Power Supply Design be an Afterthought
Webinar
0 comments
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Understanding LDOs and Their Key Performance Parameters
Technical Paper
0 comments
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Scalable Industrial Ethernet to Accelerate Industry 4.0
Webinar
0 comments
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Raising the Efficiency of Power-Factor Correction, from Standby to Full Load
Technical Paper
0 comments
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Providing a fully digitalized strategy that integrates PCB and mechanical flows
Technical Paper
0 comments
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Dual 13A μModule Regulator with Digital Interface for Remote Monitoring and Control of Power
Technical Paper / Application Note
0 comments
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Doing More with Buck Regulator ICs
Technical Paper
0 comments
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Stay Ahead of Efficiency Regulations for Power Adapters
Technical Paper
0 comments
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Inside a New Architecture for USB Type-C Applications
Technical Paper
0 comments
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Aligning Automotive Safety Requirements Between IP and SoCs
Technical Paper
0 comments
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Rugged IO-Link Solutions
Technical Paper / Product Paper
0 comments
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Fundamentals of Choosing Power-Distribution Topologies and Regulators
Course
1 comments
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Control the Voltage of a Remote Load over Any Length of Copper Wire
Technical Paper / Application Note
0 comments
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60V, Synchronous Step-Down High Current LED Driver
Technical Paper / Application Note
0 comments
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Security for the Connected World with Renesas MCUs
Course
0 comments
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A Paradigm Shift in Benchmarking Wi−Fi Performance
Technical Paper
0 comments
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42V Quad Monolithic Synchronous Step-Down Regulator with 30μA Quiescent Current
Technical Paper
0 comments
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How to Charge Capacitive Loads with eFuses
Technical Paper
0 comments
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Industry's First 0.8uVRMS Noise LDO Has 79dB Power Supply Rejection Ratio at 1MHz
Technical Paper / Application Note
0 comments
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The Designer’s Guide to: Common Considerations When Selecting a MHz Crystal
Technical Paper
0 comments
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New Linear Regulators Solve Old Problems
Technical Paper / Product Paper
0 comments
Regulation
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Topics
- Analog/Mixed Signal (11)
- Components | Packaging (1)
- Digital Processing (50)
- EDA | IP (24)
- I/O (3)
- Power | Power Management (97)
- RF/Wireless (4)
- Software (1)
- Storage (9)
- Test | Measurement (0)
- Tools | Development (9)
Industry
- Automotive/Transportation (2)
- Communications and Networking Systems or Equipment (1)
- Computers and Peripherals (3)
- Consumer Electronics & Appliances (1)
- Aerospace/Defense/Government (1)
- Industrial/Robotics/Motor Control (0)
- Electronic Instrumentation or Test (0)
- Medical Devices & Systems (0)
- Semiconductor Design & Manufacturing (0)
- Security (1)
- Academia (0)
- Commercial/Retail (0)
- Energy (0)
- Other (0)
Date Range
Design Practices and Strategies for Efficient Signal Integrity Closure
Technical Paper
144 KB
Posted on: Nov 12, 2004
0 likes
Power Management in Complex SoC Design
Technical Paper
438 KB
Posted on: Nov 16, 2004
0 likes
Hierarchical Design Techniques
Technical Paper
212 KB
Posted on: Nov 18, 2004
0 likes
Designing Using the AMBA 3 AXI Protocol
Technical Paper
269 KB
Posted on: Apr 28, 2005
1 likes
Size Matters! How a System Perspective Slashes the Size of a USB 2.0 Device Core
Technical Paper
755 KB
Posted on: Jul 17, 2002
0 likes
Discovery AMS Full-Chip Verification of Mixed-Signal Designs
Technical Paper
656 KB
Posted on: Oct 5, 2004
0 likes
A Reference Verification Methodology for Vera
Technical Paper
98 KB
Posted on: Oct 6, 2004
0 likes
Integration of Vera and System Studio
Technical Paper
1.12 MB
Posted on: Oct 6, 2004
0 likes
Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
Technical Paper
Posted on: Mar 20, 2006
0 likes
Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
Technical Paper
91 KB
Posted on: Mar 20, 2006
0 likes
SystemVerilog for e Experts—Understanding the Migration Process
Technical Paper
161 KB
Posted on: May 26, 2006
0 likes
Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design
Technical Paper
87 KB
Posted on: Sep 29, 2006
0 likes
Efficient Development of Wireless IP with High Level Modeling and Synthesis
Technical Paper
237 KB
Posted on: Jun 29, 2006
0 likes
Infusing Speed and Visibility into ASIC Verification
Technical Paper
669 KB
Posted on: Jan 5, 2007
0 likes
Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies
Technical Paper
193 KB
Posted on: Jun 19, 2008
0 likes
Life Begins at 65—Unless You Are Mixed Signal?
Technical Paper
376 KB
Posted on: Jul 28, 2008
0 likes
DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs
Technical Paper
847 KB
Posted on: May 19, 2008
0 likes
HapsTrak — A Key to Success
Technical Paper
731 KB
Posted on: Nov 1, 2007
0 likes
Synopsys Eclypse Low Power Solution
Technical Paper
887 KB
Posted on: Dec 17, 2008
0 likes
System Level Performance Analysis with Formal Methods and Virtual Prototyping
Technical Paper
2.40 MB
Posted on: Sep 26, 2008
0 likes
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