Multicore CPU handles computational needs of high-definition video codec

Telairity Semiconductor multicore video processor handles the demanding computational requirements of the H.264 (MPEG-4 Part 10) high-definition codec. The programmable Telairity-1 architecture combines five independent vector/scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3 Gbps in a single multicore SoC.