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Optimizing SMIC 40LL and 40ULP Designs for Speed and Energy Efficiency

Original Air Date: Feb 7, 2018 Webinar
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Combining SMIC processes with DesignWare Embedded Memories and Logic Libraries, designers can achieve both high speed and low power across their entire SoC. Learn how memory compliers can leverage assist circuitry to support the lowest operating voltages, ultra-low leakage libraries can reduce leakage by up to 100X, and low voltage and multi-voltage low power libraries can save dynamic and leakage power for IoT applications.

This webinar will provide details on how foundation IP—logic libraries and embedded memories—can help designers take advantage of the power benefits available in SMIC's 40LL & 40ULP process technologies. It will describe:

  • How memory compliers can leverage assist circuitry to support the lowest operating voltages
  • How ultra-low leakage libraries can be used to build always-on logic blocks, reducing leakage by up to 100X
  • How low voltage and multi-voltage low power libraries can save dynamic and leakage power for IoT applications

Who should attend: Designers and design managers of low-power, high-performance IoT and mobile applications

Speakers

Ken Brock, Product Marketing Manager for Logic Libraries, Synopsys

Ken Brock is Product Marketing Manager for Logic Libraries at Synopsys and brings 25 years of experience in the field. Prior to Synopsys, Ken held marketing positions at Virage Logic, Silvaco, Virtual Silicon, Compass Design Systems, Mentor Graphics and Silicon Compilers. Ken holds a Bachelor's Degree in Electrical Engineering and an MBA from Fairleigh Dickinson University.



Namil Jeon Sr., Director of Design Services, SMIC

Namil Jeon brings more than 20 years of experience to his role as Sr. Director of Design Services at SMIC. Prior to SMIC, Namil held SoC and ASIC Design position at LG Semicon, LG Electronics, Avanti and AL Tech. Namil holds a Bachelor's Degree in Electrical Engineering from SungKyunKwan University.

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