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Increase LVS verification productivity in early design cycles

Authored on: Jul 31, 2020 by Raghav Katoch

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Introducing Calibre nmLVS-Recon, which gives designers a systematic methodology for prioritizing and resolving high-impact circuit issues in early design stages. Learn more about the short isolation (SI) use model that focuses on short isolation and short paths debugging, with three built-in options for analyzing specific areas.

  • Provides targeted short isolation analysis and debugging on incomplete/immature blocks, macros, and chips during early design phases
  • Allows designers to run multiple fast iterations of short isolation analysis and debugging, speeding up overall time to tapeout
  • Designers can partition designs by layer type, layer groups, or net type to support error prioritization

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