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Deep Data Analytics for High Bandwidth Memory (HBM) Reliability

Authored on: May 6, 2020

Technical Paper

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Visibility of HBM subsystems is limited by nature due to its 3D integration technology, and signal integrity problems are difficult to debug, validate and monitor. Multi-die HBM packaging introduces new reliability challenges which can lead to functional device failures in-field. In addition, an HBM PHY does not allow for redundancies due to the high-density routing, and one u-bump per signal is used for the entire HBM connectivity. In this case, a failure in any of the PHY or HBM u-bumps will lead to a chip operational failure.

This whitepaper presents the use of proteanTecs Deep Data analytics for HBM reliability monitoring. It describes the operation concept and provides results from a GUC 7nm HBM Controller ASIC.

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