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IC Design: Preparing for the Next Node

Authored on: Mar 1, 2019 by David Abercrombie, Michael White

Technical Paper

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Despite the rumors of Moore's law dying or falling behind, it seems that most of the semiconductor industry continues to push forward to new process nodes and increasingly complex designs. The challenges of preparing for the next node are truly immense for the foundries, the design companies and the EDA industry as a whole. Faced with increased computational challenges, the EDA community must look to strong partnerships, continued optimization and new technologies to prepare for the future. Although rarely discussed, the EDA industry is also constantly in a state of preparing for the next node. All those new process technologies and new design functionality add up to an ever-increasing pressure for increased automation in verification using a set of foundry-qualified tools, all while maintaining the highest level of accuracy without driving up runtimes. Read this paper to learn more.


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