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Verifying the True Jitter Performance of Clocks in High-speed Digital Designs

Authored on: Apr 8, 2020

Technical Paper / Product Paper

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As the data rates in high-speed digital designs increase, the limits for overall system jitter become tighter. The R&S®FSWP offers the functionality needed to test low-jitter clocks in both SSC OFF mode and SSC ON mode. It provides very high AM suppression in the phase noise measurement and excellent phase noise sensitivity for precise jitter measurements on low-jitter clocks for modern high-speed digital designs.

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