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New SI Techniques for Large System Performance Tuning

Authored on: Mar 17, 2016 by Donald Telian, Michael Steinberger, Barry Katz

Technical Paper / Conference Paper

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Large systems with multiple configuration options and extended product lifecycles provide performance tuning opportunities such as SerDes setting optimizations and manufacturing improvements. This paper describes newly-developed techniques for equalization tuning and discontinuity reduction, offering additional design margin. Cost reductions are also achieved as new Signal Integrity (SI) techniques demonstrate performance parity removing non-essential re-timers and PCBs layers. This is the fourth in a series of DesignCon papers detailing the design and implementation of a system characterized by multiple thousands of interconnected serial links spanning dozens PCBs, operating at 3rd and 4th generation serial link data rates (6 to 12 Gbps).

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