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Optimizing DDR Memory Subsystem Efficiency Part 1: The Unpredictable Memory Bottleneck

Authored on: Jan 16, 2016 by Tim Kogel

Technical Paper

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The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. This white paper covers part 1 of our story, describing challenges and the benefits of using virtual prototyping tools and best practice techniques to optimize the DDR memory controller configuration for your SoC application. In a second white paper we will cover part 2, how to use Synopsys Platform Architect MCO tools and models to apply these best practices to optimize a hypothetical Mobile Application Processor case study design.

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