Welcome Guest

Best Practices for Low Power RTL Design

Authored on: Oct 2, 2015 by Preeti Gupta

Technical Paper

0
More InfoLess Info

Smart devices and smartly-connected IoT devices, cloud computing and big data, device integration and fabrication technology all continue to drive power budgeting, energy and thermal efficiency for IP and SoC semiconductor design. Early visibility to power can drive power-related architectural design decisions early in the flow for the highest impact. Managing power at RTL (Register Transfer Level) has emerged as a reliable, high-performance, high-coverage, and high-capacity alternative to traditional gate-level netlist based power methodology. This paper focuses on designing power-efficient RTL through a set of prevalent best practices including early power budgeting, analysis, reduction and regressions.

I want to receive emails about webinars, products, and offers from ANSYS & ANSYS Partners. You may receive a request for your feedback from ANSYS. Read our new Privacy Policy to understand what data we collect, why we collect it, and what we do with it.

View
 
Please Login

You will be redirected to the login page

×
Please Login

You will be redirected to the login page

×
Please Login

You will be redirected to the login page