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Leveraging HyperFlex Architecture in Stratix 10 Devices to Achieve Maximum Power Reduction

Authored on: Jun 8, 2015 by Martin S. Won

Technical Paper

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Readers will learn how Stratix 10 FPGAs and SoCs, developed on Intel’s industry leading 14 nm Tri-Gate process, offers the lowest power in the industry. The paper describes in detail advanced power features and capabilities for power reduction including SmartVID, hard IP blocks for commonly used functions and floating-point DSP processing, power gating of unused blocks, low-power transceivers, and extra low-voltage and extra low-static power devices.

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