Optimizing cost and performance with 3D chip/package/board co-design
The increasing complexity of SoCs ,with a new generation of designs that combine multiple chips in a single package, is creating new challenges in the design of packages, PCBs, and ICs. The process typically involves three independent design processes—chip, package and PCB—carried out with point tools whose interface requires time-consuming manual processes prone to error and limit the potential for reuse. This challenge is being addressed by a new integrated 3D chip/package/board co-design environment which makes it possible to holistically optimize the package, board and IC design to a greater degree by considering the system-level impact of each design decision. Read this paper to learn more.