Welcome Guest

Formal Verification of Power-Aware Designs Using JasperGold Low Power Verification App

Authored on: May 1, 2013 by Lawrence Loh

Technical Paper / Product Paper

0
More InfoLess Info

Power reduction and management methods are now all-pervasive in system-on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design, through RTL implementation to physical design.

View
 
Please Login

You will be redirected to the login page

×
Please Login

You will be redirected to the login page

×
Please Login

You will be redirected to the login page