Welcome Guest

3D-IC Testing with the Mentor Graphics Tessent Platform

Authored on: Apr 1, 2011 by Steve Pateras

Technical Paper

1
More InfoLess Info

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time. The migration to 3D-ICs connected by TSVs presents three new test challenges to the industry. This white paper will address these challenges.

View
 
Please Login

You will be redirected to the login page

×
Please Login

You will be redirected to the login page

×
Please Login

You will be redirected to the login page